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Features
* * * * * * * * * * * * *
Supply Voltage up to 40V RDSon Typically 0.8 at 25C, Maximum 1.5 at 150C Up to 1.0A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable of Switching all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors No Shoot-through Current Very Low Quiescent Current IS < 5 A in Standby Mode versus Total Temperature Range Outputs Short-circuit Protected Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency SO14 Power Package
1. Description
The ATA6826 is a fully protected Triple Half-bridge designed in Smart Power SOI Technology, used to control up to 3 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 1.0A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode opens a wide range of applications. Automotive qualification gives added value and enhanced quality for exacting requirements of automotive applications.
Triple Half-bridge DMOS Output Driver with Serial Input Control ATA6826
4834D-BCD-10/07
Figure 1-1.
Block Diagram
n. u.
n. u.
O C S
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
H S 3
L S 3
H S 2
L S 2
H S 1
L S 1
S R R
3
VS
Input register Output register
DI 5 P S F O P L S C D n. u. n. u. n. u. n. u. n. u. n. u. H S 3
Serial interface
L S 3 H S 2 L S 2 H S 1 L S 1 T P
Charge pump
CLK 6
CS 4 Fault detect INH 10 Fault detect Fault detect
UV protection
11
Control logic
VCC
DO 9
Power-on reset
1 7
GND GND GND GND
Fault detect
Fault detect
Fault detect
Thermal protection
13 OUT1
8 14
2 OUT3
12 OUT2
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2. Pin Configuration
Figure 2-1. Pinning SO14
GND OUT3 VS CS DI CLK GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND OUT1 OUT2 VCC INH DO GND
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Description
Symbol GND OUT3 VS CS DI CLK GND GND DO INH VCC OUT2 OUT1 GND Function Ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3 with internal reverse diodes; short-circuit protection; overtemperature protection; diagnosis for short and open load Power supply for output stages OUT1, OUT2 and OUT3, internal supply Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5 V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Ground; see pin 1 Ground; see pin 1 Serial data output; 5V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line. Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation Logic supply voltage (5V) Half-bridge output 2; see pin 2 Half-bridge output 1; see pin 2 Ground; see pin 1
3
4834D-BCD-10/07
3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1.
CS
Data Transfer
DI
SRR
LS1
HS1
LS2
HS2
LS3
HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OCS 13
n. u.
n. u.
0 CLK
1
2
3
4
5
6
7
8
9
10
11
12
14
15
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
SCD
OPL
PSF
Table 3-1.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input Data Protocol
Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u. Function Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Overcurrent shutdown (high = overcurrent shutdown is active) Not used Not used
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Table 3-2.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13
Output Data Protocol
Output (Status) Register TP Status LS1 Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. SCD Function Temperature prewarning: high = warning High = output is on, low = output is off; not affected by SRR High = output is on, low = output is off; not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted switch. Open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. Power-supply fail: undervoltage at pin VS detected
14 15
OPL PSF
After power-on reset, the input register has the following status:
Bit 15 Bit 14 x x Bit 13 (OCS) H Bit 12 x Bit 11 x Bit 10 x Bit 9 x Bit 8 x Bit 7 x Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 Bit 1 (HS1) (LS1) L L Bit 0 (SRR) L
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation.
Bit 15 Bit 14 H H H H H H Bit 13 (OCS) H H H Bit 12 H L L Bit 11 H L L Bit 10 L H L Bit 9 L H L Bit 8 L L H Bit 7 L L H Bit 6 (HS3) L L L Bit 5 (LS3) L L L Bit 4 (HS2) L L L Bit 3 (LS2) L L L Bit 2 Bit 1 (HS1) (LS1) L L L L L L Bit 0 (SRR) L L L
5
4834D-BCD-10/07
3.2
Power-supply Fail
In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR (Status Register Reset) bit in the input register.
3.3
Open-load Detection
If the current through a high-side or low-side switch in the ON-state stays below the open-load detection threshold, the open-load detection bit (OPL) in the output register is set. The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to be longer than the open-load detection delay time tdSd.
3.4
Overtemperature Protection
If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T jPW set , the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations.
3.5
Short-circuit Protection
The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled.
3.6
Inhibit
Applying 0V to pin 10 (INH) inhibits the ATA6826. All output switches are then turned off and switched to tri-state. The data in the output register is deleted. The current consumption is reduced to less than 5 A at pin VS and less than 25 A at pin VCC. The output switches can be activated again by switching pin 10 (INH) to 5V which initiates an internal power-on reset.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Supply voltage Supply voltage t < 0.5s; IS > -2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Output voltage Reverse conducting current (tpulse = 150 s) Junction temperature range Storage temperature range Pin 3 3 11 4 to 6, 10 9 4 to 6, 10 9 2, 12 and 13 2, 12 and 13 2, 12 and 13 towards pin 3 Symbol VVS VVS VVCC VCS,VDI, VCLK, VINH VDO ICS,IDI, ICLK, IINH IDO IOut3, IOut2, IOut1 IOut3, IOut2, IOut1 IOut3, IOut2, IOut1 TJ TSTG Value -0.3 to +40 -1 -0.3 to +7 -0.3 to VVCC + 0.3 -0.3 to VVCC + 0.3 -10 to +10 -10 to +10 Internally limited, see output specification -0.3 to +40 17 -40 to +150 -55 to +150 V A C C Unit V V V V V mA mA
5. Thermal Resistance
Parameters ATA6826 Junction pin Junction ambient Measured to GND Pins 1, 7, 8 and 14 RthJP RthJA 30 65 K/W K/W Test Conditions Symbol Value Unit
6. Operating Range
Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Note: Threshold for undervoltage detection Symbol VVS VVCC VCS,VDI, VCLK, VINH fCLK Tj Value VUV(1) to 40 4.75 to 5.25 -0.3 to VVCC 2 -40 to +150 Unit V V V MHz C
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4834D-BCD-10/07
7. Noise and Surge Immunity
Parameters Conducted interferences Interference suppression ESD (Human Body Model) CDM (Charged Device Model) Note: Test pulse 5: Vsmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 ESD S 5.1 AEC-Q100 Value Level 4(1) Level 5 2 kV 750V corner pins 500V all other pins
8. Electrical Characteristics
7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; -40C < Tj < 150 C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3a 2.3b 2.4 2.5 3 3.1 3.2 3.3 Parameters Current Consumption Quiescent current VS VVS < 20V, INH = low 3 11 3 11 3 3 IVS IVCC IVS IVCC IVS IVS 0.5 2.5 1 15 4 350 5 25 6 500 5.5 10 A A mA A mA mA A A A A A A 4.75 V < VVCC < 5.25V, Quiescent current VCC INH = low Supply current VS Supply current VCC Discharge current VS Discharge current VS VVS < 20V normal operating, all outputs off 4.75V < VVCC < 5.25V, normal operating VVS = 32.5V, INH = low VVS = 40V, INH = low Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Undervoltage Detection, Power-on Reset Power-on reset threshold Power-on reset delay time After switching on VCC 3 3 3 11 VVCC tdPor VUv VUv VUv tdUV 10 3.2 30 5.6 6.0 0.6 40 3.9 95 4.4 190 6.5 7.0 V s V V V s A A A A A A
Undervoltage-detection VCC = 5V threshold (down) Undervoltage-detection VCC = 5V threshold (up) Undervoltage-detection VCC = 5V hysteresis Undervoltage-detection delay time Thermal Prewarning and Shutdown Thermal prewarning set Thermal prewarning reset Thermal prewarning hysteresis
TjPW set TjPW reset TjPW
120 105
145 130 15
170 155
C C C
B B B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms
8
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ATA6826
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; -40C < Tj < 150 C; unless otherwise specified, all values refer to GND pins. No. 3.4 3.5 3.6 Parameters Thermal shutdown off Thermal shutdown on Thermal shutdown hysteresis Ratio thermal shutdown off/thermal prewarning set Ratio thermal shutdown on/thermal prewarning reset Output Specification (OUT1-OUT3) IOut 1-3 = -0.9A On resistance 4.2 4.3 4.4 High-side output leakage current Low-side output leakage current High-side switch reverse diode forward voltage IOut 1-3 = +0.9A VOut 1-3 = 0V, output stages off VOut 1-3 = VVS, output stages off IOut 1-3 = 1.5A 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 2, 12, 13 RDSOn1-3 RDSOn1-3 IOut1-3 IOut1-3 VOut1-3 - VVS VOut 1-3 IOut1-3 -2 -1.7 -2.0 1 1 10 -50 10 200 -30 30 -1.3 -1.3 1.3 1.3 -1.0 -1.0 1.7 2.0 40 -10 50 600 20 20 -15 200 0.8 0.8 1.5 1.5 A A A A A A Test Conditions Pin Symbol Tj switch off Tj switch on Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset 1.05 Min. 150 135 Typ. 175 160 15 Max. 200 185 Unit C C K Type* B B B
3.7
1.2
B
3.8 4 4.1
1.05
1.2
B
4.5
2
V
A
4.6
Low-side switch reverse IOut 1-3 = -1.5A diode forward voltage High-side overcurrent 7.5V < VS < 20V limitation and shutdown 20V VS < 40V threshold Low-side overcurrent 7.5V < VS < 20V limitation and shutdown 20V VS < 40V threshold Overcurrent shutdown delay time High-side open-load detection threshold Low-side open-load detection threshold Open-load detection delay time High-side output switch VVS = 13V RLoad = 30 on delay(1) Low-side output switch VVS = 13V on delay(1) RLoad = 30
V A A A A s mA mA s s s
A
4.7
A
4.8
IOut1-3 tdSd
A
4.9 4.10 4.11 4.12 4.13 4.14
A A A A A A
2, 12, 13 2, 12, 13
IOut1-3 IOut1-3 tdSd tdon tdon
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms
9
4834D-BCD-10/07
8. Electrical Characteristics (Continued)
7.5V < VVS < 40V; 4.75V < VVCC < 5.25V; INH = High; -40C < Tj < 150 C; unless otherwise specified, all values refer to GND pins. No. 4.15 4.16 Parameters Test Conditions Pin Symbol tdoff tdoff tdon - tdoff 1 Min. Typ. Max. 20 3 Unit s s Type* A A High-side output switch VVS = 13V off delay(1) RLoad = 30 Low-side output switch VVS = 13V off delay(1) RLoad = 30 Dead time between corresponding highand low-side switches Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pin DI, CLK, INH Pull-up current Pin CS VDI, VCLK, VINH = VCC VCS = 0V VVS = 13V RLoad = 30
4.17 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 7 7.1
s
A
Logic Inputs DI, CLK, CS, INH 4-6, 10 4-6, 10 4-6, 10 5, 6, 10 4 VIL VIH VI IPD IPU 50 10 -65 0.3 x VVCC 0.7 x VVCC 700 65 -10 V V mV A A A A B A A
Serial Interface - Logic Output DO Output-voltage low level IDOL = 2 mA Output-voltage high level Leakage current (tri-state) Inhibit Input - Timing Delay time from standby to normal operation tdINH 100 s A IDOL = -2 mA VCS = VCC 0V < VDO < VVCC 9 9 9 VDOL VDOH IDO VVCC -0.7V -10 10 0.4 V V A A A A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms
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9. Serial Interface - Timing
No. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Parameters Test Conditions Pin 9 9 9 9 9 4 4 4 6 6 6 6 6 5 5 Timing Chart No.(1) 1 2 10 4 8 9 5 6 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Type* D D D D D D D D D D D D D D D DO enable after CS CDO = 100 pF falling edge DO disable after CS CDO = 100 pF rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CDO = 100 pF CDO = 100 pF CDO = 100 pF
8.10 CLK low time 8.11 CLK period time 8.12 CLK setup time 8.13 CLK setup time 8.14 DI setup time 8.15 DI hold time
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. See Figure 9-1 on page 12 "Serial Interface Timing with Chart Numbers"
11
4834D-BCD-10/07
Figure 9-1.
Serial Interface Timing with Chart Numbers
1 2
CS
DO
9
CS
4
7
CLK
5 3 6 8
DI
11
CLK
10
12
DO
Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC
12
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10. Application Circuit
Figure 10-1. Application Circuit
VCC
U5021M Watchdog
Trigger Reset
Enable
VS
n. u. n. u. O C S n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R
3
VS
BYT41D
VBatt
Input register Output register Serial interface
n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1
Charge pump
Microcontroller
DI
5
P S F
O P L
S C D
n. u.
n. u.
CLK
6
CS
4
Fault detect Fault detect Fault detect
UV protection
11
INH
10
Control logic
VCC
DO
9
1 GND 7 GND
Fault detect
Fault detect
Fault detect
Thermal protection
2
OUT3
8 14
GND GND
12
OUT2
13
OUT1
VCC
M
11. Application Notes
M
It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. The value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see "Absolute Maximum Ratings" on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins.
4834D-BCD-10/07
+
Power-on reset
+
13 V
VCC VCC
5V
13
12. Ordering Information
Extended Type Number ATA6826-TUSy ATA6826-TUQy Package SO14 SO14 Remarks Power package, tubed, lead-free Power package, taped and reeled, lead-free
13. Package Information
Package SO14
Dimensions in mm
8.75 5.2 4.8 3.7
1.4 0.4 1.27 7.62 14 8 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
1
7
14. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4834D-BCD-10/07 History * Put datasheet in a new template * Section 8 "Electrical Characteristics" number 2.3 on page 8 changed
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ATA6826
4834D-BCD-10/07
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4834D-BCD-10/07

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